Triple Metal Surrounding Gate Junctionless Tunnel FET Based 6T SRAM Design for Low Leakage Memory System

SEU sensitivity of Junctionless Single-Gate SOI MOSFETs-based 6T SRAM cells investigated by 3D TCAD simulation

Article history: Received 25 May 2015 Received in revised form 20 June 2015 Accepted 24 June 2015 Available online xxxx

Novel Subthreshold and Gate Leakage Reduction Techniques for 6T-SRAM Cell

Power has been an important issue for the present day microelectronic circuits of Soc designs. In the entire phase of design controlling power and dealing with power dissipation is very important. There are six leakage components in a MOS transistor. About 50 % of the total power consumption is through leakage components alone. Out of this 40 % power dissipation is through transistors.Out of th...

Sram System Design for Memory Based Computing

Analysis of Leakage Power Reduction in 6T SRAM Cell

On chip cache memories contributes a large fraction to the total power consumption of microprocessor. As technology scales down into d e e p -submicron, leakage power is becoming a dominant source of power consumption. As cache memory is an array structure leakage reduction in just one memory cell can on the whole reduce a large amount of leakage power. In this thesis leakage power of conventio...

Ambipolar Effect Free Double Gate PN Diode Based Tunnel FET